The present invention relates to an integrated circuit device having stacking wafers with through silicon vias and a method for preparing the same. More particularly, the present invention relates to an integrated circuit device and method for preparing the same by bonding wafers before the formation of the through silicon via.
Packaging technology for integrated circuit structures has been continuously developed to meet the demand for miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric and electronic products are required, various techniques have been disclosed in the art.
By using a stack of at least two chips, i.e., the so-called 3D package, in the case of a memory device for example, it is possible to produce a product having a memory capacity which is twice as large as that obtainable through semiconductor integration processes. Also, a stack package provides advantages not only of an increase in memory capacity but also in regards to mounting density and mounting area utilization efficiency. Due to such advantages, research and development of stack package technology has accelerated.
As an example of a stack package, a through-silicon via (TSV) has been disclosed in the art. The stack package using a TSV has a structure in which the TSV is disposed in a chip so that chips are physically and electrically connected with each other through the TSV. Generally, a TSV is formed by etching a vertical via through a substrate and filling the via with a conductive material, such as copper. To increase the transmission speed and for high-density fabrication, the thickness of a semiconductor wafer comprising multiple integrated circuit structures each having the TSV should be reduced.
U.S. Pat. No. 7,683,459 discloses a hybrid bonding method for through silicon via based wafer stacking, in which patterned adhesive layers are provided to join together adjacent wafers in the stack, while solder bonding is used to electrically connect the lower end of the via in the upper wafer to the bump pad on the upper end of the via in the lower wafer. However, the formation of the bump pad on the upper end of the via requires seeding, electroplating, photolithography and etching processes; therefore, the formation of the bump pad on the upper end of the via is very complicated and expensive.